Processes and Experiences in VHDL Top Down Design
نویسنده
چکیده
Described are VHDL related methods and experiences from the RASSP programs model year effort. The "Virtual Prototype” development methodology is presented highlighting specific VHDL model views and their interact ions with sof tware design. Performance and Instruction Set Archi tec ture model ing areas o f the methodology are elaborated drawing from the experiences of the Demonstration team. Finally, ongoing work with multithreaded operating system and cycle based VHDL simulators is explored as CAE technology solutions for growing design and analysis complexity.
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